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RISC

Authors -- Milind Nagda, Govind  & Ganesh Pai [won second prize in branch contest]

ABSTRACT

The primary aim of any microprocessor architecture is to improve its performance relative to earlier designs. This has evoked a radical re-thinking and re-evaluation of the concepts of conventional microprocessor architecture design, leading to the Reduced Instruction-Set Computer (RISC) architecture design paradigm. A RISC microprocessor is designed to perform a smaller number of types of computer instructions so that it can operate at a higher speed performing more Millions of Instructions Per Second (MIPS). In this paper, we briefly introduce the Complex Instruction-Set Computer (CISC) architecture. Then, we present a comprehensive analysis of the RISC philosophy, focussing primarily on its architecture and on its essential characteristics that differentiate it from the CISC architecture. Finally, we discuss typical RISC models with the help of two actually implemented architectures: The IBM RS/6000 and the Intel i860, and conclude with a note on newer avenues in microprocessor architecture design, such as Post-RISC.

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Last Updated : September 03, 1999 09:47:05 AM -0400

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